? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14598b/d mc14598b 8-bit bus-compatible latches the mc14598b is an 8bit latch addressed with an external binary address. the 8 latchoutputs are high drive, threestate and bus line compatible. the drive capability allows direct applications with mpu systems such as the motorola 6800 family. the latches of the mc14598b are accessed via the address pins, a0, a1, and a2. all 8 outputs from the latches are available in parallel when enable is in the low state. data is entered into a selected latch from the data pin when the strobe is high. master reset is available on both parts. ? serial data input ? threestate bus compatible parallel outputs ? threestate control pin (enable ) ttl compatible input ? open drain full flag (multiple latch wireo ring) ? master reset ? level shifting inputs on all except enable ? diode protection e all inputs ? supply voltage range e 3.0 vdc to 18 vdc ? capable of driving ttl over rated temperature range with fanout as follows: 1 ttl load 4 lsttl loads maximum ratings (voltages referenced to v ss ) (note 1.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in input voltage range, enable (dc or transient) 0.5 to v dd + 0.5 v v in input voltage range, all other inputs (dc or transient) 0.5 to v dd + 12 v v out output voltage range, (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 2.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 1. maximum ratings are those values beyond which damage to the device may occur. 2. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14598bcp pdip18 20/rail marking diagrams 1 18 pdip18 p suffix case 707 mc14598bcp awlyyww this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid ap- plications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused out- puts must be left open.
mc14598b http://onsemi.com 2 pin assignment nc data reset d0 v ss a1 a0 strobe enable d3 d2 d1 v dd a2 d7 d6 d5 d4 14 15 16 17 18 10 11 12 13 5 4 3 2 1 9 8 7 6 block diagrams mc14598b enable outputs 1 high impedance 0d n d n = state of nth latch output truth table nc = no connection 1 17 16 15 14 13 12 11 d0 d1 d2 d3 d4 d5 d6 d7 enable 4 three state output buffers 8 latches address decoder v dd = 18 v ss = 9 2 3 6 reset data strobe a0 a1 a2 7 8 10
mc14598b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (3.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage (4.) e enable a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 0.8 1.6 2.4 e e e 1.1 2.2 3.4 0.8 1.6 2.4 e e e 0.8 1.6 2.4 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 2.0 6.0 10 e e e 2.0 6.0 10 1.9 3.1 4.3 e e e 2.0 6.0 10 e e e vdc input voltage a0o level other inputs (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc (v o = 0.5 or 4.5 vdc) a1o level (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current source (full e sink only) (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 10 1 5 1.0 e e e e 1.0 e e 2.0 6.0 12 e e e 1.0 e e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 1.6 e e e e e 1.6 e e 3.2 6.0 12 e e e 1.6 e e e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc threestate leakage current i tl 15 e 0.1 e 0.00001 0.1 e 3.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current at an ** external load capacitance of ** 130 pf (4.) i t 5.0 10 i t = (2.0 m a/khz) f + i dd i t = (4.0 m a/khz) f + i dd i t = (6.0 m a/khz) f + i dd m adc 3. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 4. the formulas given are for the typical characteristics only at 25 c.
mc14598b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (5.) (t a = 25 c, c l = 130 pf + 1 ttl load) v dd all types characteristic symbol v dd vdc min typ (6.) max unit output rise and fall time t tlh , t thl = (0.5 ns/pf) c l + 35 ns t tlh , t thl = (0.2 ns/pf) c l + 25 ns t tlh , t thl = (0.16 ns/pf) c l + 20 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time enable to output t plh , t phl 5.0 10 15 e e e 160 125 100 320 250 200 ns strobe to output 5.0 10 15 e e e 200 100 80 400 200 160 reset to output 5.0 10 15 e e e 175 90 70 350 180 140 pulse width enable t wh , t wl 5.0 10 15 320 240 160 160 120 80 e e e ns strobe 5.0 10 15 200 100 80 100 50 40 e e e increment 5.0 10 15 200 100 80 100 50 40 e e e reset 5.0 10 15 300 160 100 150 80 50 e e e setup time data t su 5.0 10 15 100 50 35 50 25 20 e e e ns address 5.0 10 15 200 100 70 100 50 35 e e e hold time data t h 5.0 10 15 100 50 35 50 25 20 e e e ns address 5.0 10 15 100 50 35 50 25 20 e e e reset removal time t rem 5.0 10 15 20 20 20 25 15 10 e e e ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
mc14598b http://onsemi.com 5 mc14598b function diagram enable 4 reset 2 strobe6 data3 to other latches v dd v ss each latch zero select 1d0 17d1 16d2 15d3 14d4 13d5 12d6 11d7 address decoder additional 7 latches a07 a18 a210 to other latches (m.s.b) mc14598b timing diagram *1.4 v with v dd = 5.0 v notes: 1. highimpedance output state (another device controls bus). 2. output load as for mc14597b. d7 reset a0, a1, a2 data strobe enable 90% 10% 50% 50% t phl t plh 1 t thl t plh 90% 10% t tlh t w 50% 20 ns 90% 10% t su t h t h t su 90% 10% 50% 90% 10% 20 ns t w 20 ns t w *
mc14598b http://onsemi.com 6 truth table for mc14597b address increment enable reset counter full x 1 count up e x 1 no change e x 1 0 reset to zero set to one x 0 1 no change set to one if at to zero on x 1 1 address 7 falling edge of strobe x = don't care latch truth table address other strobe reset latch latches 01 * * 1 1 data * x0 0 0 *= no change in state of latch x = don't care test load all outputs d n +5.0 v r l = 2.5 k 11.7 k 130 pf circuit diagrams external to or containing motorola products are included as a means of illustration only. complete information sufficient for construction purposes may not be fully illustrated. although the information herein has been carefully checked and is believed to be reliable. motorola assumes no responsibility for inaccuracies. information herein does not convey to the purchaser any license under the patent rights of motorola or others. the information contained herein is for guidance only, with no warranty of any type, expressed or implied. motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time.
mc14598b http://onsemi.com 7 package dimensions pdip18 p suffix plastic dip package case 70702 issue c notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. controlling dimension: inch. 1 seating plane 10 9 18 m a b k c n f g d h j l dim min max min max millimeters inches a 22.22 23.24 0.875 0.915 b 6.10 6.60 0.240 0.260 c 3.56 4.57 0.140 0.180 d 0.36 0.56 0.014 0.022 f 1.27 1.78 0.050 0.070 g 2.54 bsc 0.100 bsc h 1.02 1.52 0.040 0.060 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040
mc14598b http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14598b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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